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CUSTOMER PROCUREMENT SPECIFICATION
1
Z86C83/C84
Z8(R) MCU MICROCONTROLLERS
FEATURES
Device Z86C83 Z86C84 ROM (KB) 4 4 RAM* (Bytes) 237 237 I/O Lines 21 17 Voltage Range 3.0V to 5.5V 3.0V to 5.5V
s
1
Six Vectored, Prioritized Interrupts from Six Different Sources Two Analog Comparator Inputs with Programmable Interrupt Polarity Two Programmable 8-Bit Timers, each with a 6-Bit Programmable Prescaler Auto Latch Mask Option for P00, P01, and P02 Power-On Reset (POR) Timer Permanent Watch-Dog Timer (WDT) Mask Option Software-Programmable Pull-Up Resistors On-Chip Oscillator for Crystal, Resonator or LC
s
Note: * General-Purpose s s s s
s
28-Pin DIP, SOIC, and PLCC Packages
s
Clock Speed: 16 MHz
s
Three Expanded Register Groups
s
8-Channel, 8-Bit A/D Converter with Track and Hold, and Unique R-Ladder AGND Offset Control Z86C84 has two 8-Bit D/A Converters Programmable Gain Stages, 3 s Settling Time with
s s
s
GENERAL DESCRIPTION
The Z86C83/C84 Consumer Controller Processors (CCPTM) are full-featured members of the CMOS Z8 microcontroller family offering a unique register-to-register architecture that avoids accumulator bottlenecks for higher code efficiency than RISC processors. The Z86C83/C84 are designed to be used in a wide variety of embedded control applications, such as appliances, process controls, keyboards, security systems, battery chargers, and automotive modules. For applications requiring powerful I/O capabilities, the Z86C83/C84 devices can have up to 21/17 (C83/C84 respectively) pins dedicated to input and output. These lines are grouped into three ports, and are configured by software to provide digital/analog I/O timing and status signals. An on-chip, half-flash 8-bit 1/2 Least Significant Bit (LSB) A/D converter can multiplex up to eight analog inputs. Unused analog inputs revert to standard digital I/O use. Unique, programmable AGND offset control of the A/D resistor ladder compresses the converter's dynamic range for maximum effective 9-bit A/D resolution. The Z86C84 has two 8-bit 1/2 LSB D/A converters. High and low reference voltages provide precise control of the output voltage range. Programmable gain for each D/A converter provides a maximum effective 10-bit resolution for many tasks. On-chip 8-bit counter/timers with many user-selectable modes simplify real-time tasks, such as counting, timing, and generation of PWM signals. The designer can prioritize six different maskable, vectored, internal or external interrupts for efficient interrupt handling and multitasking functions.
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Z86C83/C84 Z8(R) MCU Microcontrollers
GENERAL DESCRIPTION (Continued)
By means of an expanded register file, the designer has access to additional control registers for configuring peripheral functions including the A/D and D/A converters, counter/timers, and I/O port functions (Figure 1). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection
Power Ground
Circuit
VCC GND
Device
VCC VSS
P00 P01 P02 P03 Port 0 P04 P05 P06 VDHI ** VDL0 ** DAC1 ** DAC2 ** AC0/P20 AC1/P21 AC2/P22 AC3/P23 AC4/P24 AC5/P25 AC6/P26 AC7/P27
Comparators (2)
Register File 256 x 8-Bit
P31 P32 P33 Port 3 P34 P35 P36 Z8(R) Core
Register Bus Internal Address Bus ROM 4K x 8 Internal Data Bus
**Dual 8-Bit DAC
Port 2
Expanded Register File
Expanded Register Bus
Machine Timing and Instruction Control
XTAL 1/2 /RESET
Power
VCC GND
AVCC AGND
8-Channel 8-Bit A/D
Counter/Timer 8-Bit (2)
Notes: ** Not available on Z86C83. Not available on Z86C84.
Figure 1. Z86C83/C84 Functional Block Diagram
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PIN DESCRIPTION
Table 1. Z86C83 28-Pin DIP, SOIC Pin Identification* Symbol P21-P27 or AC1-AC7 8 /RESET 9 XTAL1 10 XTAL2 11 GND 12 VCC 13-15 P31-P33 16 P34 17 P36 18 P35 19-25 P0-P06 26 AGND 27 AVCC 28 P20 or AC0 No 1-7 Function Port 2, Bit 1-7 Analog In 1-7 Reset Oscillator Clock Oscillator Clock Ground Power Port 3, Bits 1-3 Port 3, Bit 4 Port 3, Bit 6 Port 3, Bit 5 Port 0, Bits 0-6 Analog Ground Analog Power Port 2, Bit 0 Analog In 0 Direction Input/Output Input Input Output Table 2. Z86C84 28-Pin DIP, SOIC Pin Identification* Symbol P21-P27 or AC1-AC7 8 /RESET 9 XTAL1 10 XTAL2 11 GND 12 VCC 13-15 P31-P33 16 P34 17 P36 18 P35 19-21 P0-P02 22 VDLO 23 VDHI 24-25 DAC2-1 26 AGND 27 AVCC 28 P20 or AC0 No 1-7 Function Port 2, Bit 1-7 Analog In 1-7 Reset Oscillator Clock Oscillator Clock Ground Power Port 3, Bits 1-3 Port 3, Bit 4 Port 3, Bit 6 Port 3, Bit 5 Port 0, Bits 0-3 D/A Ref. Volt.,Low D/A Ref. Volt.,High D/A Converter Analog Ground Analog Power Port 2, Bit 0 Analog In 0 Direction Input/Output Input Input Output
1
Input Output Output Output Input/Output
Input/Output
Input Output Output Output Input/Output Input Input Output
Note: * DIP and SOIC Pin Description and Configuration are identical.
Input/Output
Note: * DIP and SOIC Pin Description and Configuration are identical
P21/AC1 P22/AC2 P23/AC3 P24/AC4 P25/AC5 P26/AC6 P27/AC7 /RESET XTAL1 XTAL2 GND VCC P31 P32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Z86C83
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P20/AC0 AVCC AGND P06 P05 P04 P03 P02 P01 P00 P35 P36 P34 P33
P21/AC1 P22/AC2 P23/AC3 P24/AC4 P25/AC5 P26/AC6 P27/AC7 /RESET XTAL1 XTAL2 GND VCC P31 P32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Z86C84
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P20/AC0 AVCC AGND DAC1 DAC2 VDHI VDLO P02 P01 P00 P35 P36 P34 P33
Standard Mode
* Standard Mode
Figure 2. Z86C83 28-Pin DIP and SOIC Pin Configuration*
Figure 3. Z86C84 28-Pin DIP and SOIC Pin Configuration*
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PIN DESCRIPTION (Continued)
Table 3. Z86C83 28-Pin PLCC Pin Identification No 1-8 Symbol P20-P27 or AC0-AC7 9 /RESET 10 XTAL1 11 XTAL2 12 GND 13 VCC 14-16 P31-P33 17 P34 18 P36 19 P35 20-26 P00-P06 27 AGND 28 AVCC Function Port 2, Bit 0-7 Analog In 0-7 Reset Oscillator Clock Oscillator Clock Ground Power Port 3, Bits 1-3 Port 3, Bit 4 Port 3, Bit 6 Port 3, Bit 5 Port 0, Bits 0-6 Analog Ground Analog Power Direction Input/Output Input Input Output No 1-8 Table 4. Z86C84 28-Pin PLCC Pin Identification Symbol P20-P27 or AC0-AC7 9 /RESET 10 XTAL1 11 XTAL2 12 GND 13 VCC 14-16 P31-P33 17 P34 18 P36 19 P35 20-22 P00-P02 23 VDLO 24 VDHI 25-26 DAC2-DAC1 27 AGND 28 AVCC Function Port 2, Bit 0-7 Analog In 0-7 Reset Oscillator Clock Oscillator Clock Ground Power Port 3, Bits 1-3 Port 3, Bit 4 Port 3, Bit 6 Port 3, Bit 5 Port 0, Bits 0-3 D/A Ref. Volt,Low D/A Ref. Volt.,High D/A Converter Analog Ground Analog Power Direction Input/Output Input Input Output
Input Output Output Output Input/Output
Input Output Output Output Input/Output Input Input/Output Output
P23/AC3
P22/AC2
P21/AC1
P20/AC0
AGND
AVCC
P06
P23/AC3
P22/AC2
P21/AC1
P20/AC0
AGND 27
AVCC
4 P24/AC4 P25/AC5 P26/AC6 P27/AC7 /RESET XTAL1 XTAL2 5 6 7 8 9 10 11 12 GND
3
2
1
28
27
26 25 24 23 P05 P04 P03 P02 P01 P00 P35
P24/AC4 P25/AC5 P26/AC6 P27/AC7 /RESET XTAL1 XTAL2 5 6 7 8 9 10 11
4
3
2
1
28
26 25 24 23 DAC2 VDHI VDLO P02 P01 P00 P35
Z86C83 PLCC
22 21 20 19
Z86C84 PLCC
DAC1 22 21 20 19 18 P36
13 VCC
14 P31
15 P32
16 P33
17 P34
18 P36
12 GND
13 VCC
14 P31
15 P32
16 P33
17 P34
Figure 4. Z86C83 28-Pin PLCC Pin Configuration Figure 5. Z86C84 28-Pin PLCC Pin Configuration
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VCC Pin with Respect to VSS Voltage on /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Current out of VSS Maximum Current into VCC Maximum Current into an Input Pin [Note 3] Maximum Current into an Open-Drain Pin [Note 4] Maximum Output Current Sinked by Any I/O Pin Maximum Output Current Sourced by Any I/O Pin
Notes: 1. This applies to all pins except XTAL and /RESET pins and where otherwise noted. 2. There is no input protection diode from pin to VCC. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state.
Min -40 -65 -0.6 -0.3 -0.6
Max +105 +150 +7 +7 VCC+1 770 140 125
Units C C V V V mW mA mA A A mA mA
1
-600 -600
+600 +600 25 25
Notice: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 770 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = VCC x [ ICC - (sum of IOH) ] + sum of [ (VCC - VOH) x IOH ] + sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 6).
From Output Under T est
I
150 pF
Figure 6. Test Load Diagram
VDD SPECIFICATION
VDD = 3.0V to 5.5V
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CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 20 pF 20pF 20 pF
6
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DC ELECTRICAL CHARACTERISTICS
VCC Note 3 3.0V 5.5V VCL Clock Input Low Voltage 3.0V 5.5V VIH VIL VOH1 VOL1 VOL2 VRH VRl Input High Voltage 3.0V 5.5V Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V IOL IIR ICC Output Leakage Reset Input Current Supply Current 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 5.0V 5.0V 3.0V 5.5V 3.0V 5.5V .8 VCC .8 VCC TA = 0 C to +70C Min Max 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 TA = -40C to +105C Min Max 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 Typical [13] @ 25C Units Conditions 1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 0.6 0.4 1.2 1.2 .8 VCC .8 VCC VCC VCC 0.2 0.1 0.3 0.3 1.5 2.1 1.1 1.7 10 10 <1 <1 <1 <1 -25 -40 7 20 3 5 2.0 3.7 1.5 2.9 V V V V V V V V V V V V V V V V V V mV mV A VIN = OV, VCC A A A A A mA mA mA mA VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC 10 10 IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA IOL = +12 mA 8 8 8 8 8 8 Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
1
Notes
Sym Parameter VCH Clock Input High Voltage
GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3
GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 VCC VCC VCC-0.4 VCC-0.4
GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 25 25 1 1 1 1 -130 -180 20 25 7 10 4.5 8 3.4 7.0 25 25 2 2 2 2 -130 -180 20 25 7 10 4.5 8 3.4 7.0
VOFFSET Comparator Input Offset Voltage IIL Input Leakage
-1 -1 -1 -1
-1 -1 -1 -1
@ 16 MHz @ 16 MHz @ 3.58 MHz @ 8 MHz
4, 15 4, 15 4, 15 4, 15 4 4 4 4
ICC1
Standby Current
mA HALT Mode VIN = OV, VCC @ 16 MHz mA HALT Mode VIN = OV, VCC @ 16 MHz mA Clock Divide-by-16 @ 16 MHz mA Clock Divide-by-16 @ 16 MHz
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Z86C83/C84 Z8(R) MCU Microcontrollers
TA = 0 C to +70C Min Max 8 10 500 800 0 0 VCC-1.0V VCC-1.0V 8 15 -5 -8 2.0 3.3 2.2 0 0 TA = -40C to +105C Min Max 15 20 600 1000 VCC-1.5V VCC-1.5V 10 20 -7 -10 3.6 5 11 -3 -6 3.0 Typical [13] @ 25C Units Conditions 1 2 310 600 A A A A V V A A A A V OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC
2 MHz max Int. CLK Freq.
Sym Parameter ICC2 Standby Current
VCC Note 3 3.0V 5.5V 3.0V 5.5V
Notes 6,11,15 6,11,15 6,11,14, 15 6,11,14, 15 10 10 9 9 9 9 7
STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running
VICR
Input Common Mode Voltage Range Auto Latch Low Current Auto Latch High Current VCC Low-Voltage Protection Voltage
3.0 5.5 3.0V 5.5V 3.0V 5.5V
IALL IALH VLV
Notes:
1. ICC1 Typical Max Unit Freq Clock-Driven 0.3 mA 5 mA 8 MHz 2. GND = 0V. 3. 3.0V VCC voltage specification guarantees 3.3V 0.3V, and 5.5V VCC voltage specification guarantees 5.0V 0.5V. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1 = CL2 = 100 pF. 6. Same as note [4] except inputs at V . 7. The VLV increases as the temperature decreases. 8. Standard Mode (not Low EMI). 9. Auto Latch (mask option) selected. 10. For analog comparator, inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating. 12. Excludes clock pins. 13. Typicals are at VCC = 5.0V and 3.3V. 14. Internal RC selected. 15. Combined Digital and Analog VCC supply current.
CC
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AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
1
1 3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
11
Stop-Mode Recovery Source
10
Figure 7. Additional Timing
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AC ELECTRICAL CHARACTERISTICS (Continued)
Additional Timing Table (SCLK/TCLK = XTAL/2)
VCC Note 6 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
TA = 0C to +70C TA = -40C to +105C
No Symbol 1 2 3 4 5 6 7 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TfTin TwIL TwIL TwIH Twsm Tost Twdt
Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time STOP-Mode Recovery Width Spec Oscillator Startup Time Watch-Dog Timer Delay Time
12 MHz Min Max 83 83 DC DC 15 15
16 MHz Min Max DC DC 15 15
12 MHz Min Max 83 83 DC DC 15 15
Min 62.5 62.5
16 MHz Max DC DC 15 15
Units Notes ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1,3 1,3 1,2 1,2
62.5 62.5
41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
ns ns ns ns
8A 8B 9 10 11 12
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 3.0V 3.0V 3.0V
ns ns 4 4 Reg. D1 D0 ms 00 ms ms ms 25 14 ms ms 0 1 1
WDTMR 6.25
12.5 25 100 7 3 24 13
6.25
12.5 25 100 7 3 25 14
6.25
12.5 25 100 7 3 24 13
6.25
12.5 25 100 7 3
1 0 1
13
TPOR
Power On Reset Delay
3.0V 5.5V
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 0. 5. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V.
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AC ELECTRICAL CHARACTERISTICS (Continued)
Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL) TA = 0C to +70C TA = -40C to +105C 4 MHz 4 MHz Min Max Min Max Units Notes 250 250 DC DC 25 25 250 250 DC DC 25 25 ns ns ns ns ns ns ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 4,8,9 4,8,9
No Symbol Parameter 1 2 3 4 5 6 7 TpC Input Clock Period
Vcc Note 6 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
TrC,TfC Clock Input Rise & Fall Times TwC TwTinL TwTinH TpTin Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time STOP-Mode Recovery Width Spec Oscillator Startup Time
125 125 100 70 3TpC 3TpC 4TpC 4TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 5TpC 5TpC
125 125 100 70 3TpC 3TpC 4TpC 4TpC 100 100 100 70 3TpC 3TpC 3TpC 2TpC 12 12 5TpC 5TpC
TrTin, TfTin 8A TwIL 8B TwIL 9 TwIH
ns ns ns ns
10 Twsm 11 Tost
ns ns
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P33-P31). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP mode delay is on. 5. Reg. WDTMR. 6. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For XTAL and LC oscillator, and for oscillator driven by clock driver.
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AC ELECTRICAL CHARACTERISTICS
Handshake Timing Diagrams
Data In
1
Data In Valid
2 3
Next Data In Valid
/DAV (Input)
4
Delayed DAV
5 6
RDY (Output)
Delayed RDY
Figure 8. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Figure 9. Output Handshake Timing
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AC ELECTRICAL CHARACTERISTICS (Continued)
Handshake Timing Table TA = 0C to +70C TA = -40C to +105C VCC Data 12 MHz 16 MHz 12 MHz 16 MHz Note1,2 Min Max Min Max Min Max Min Max Direction 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 0 0 160 115 155 110 160 115 120 80 0 0 42 42 0 0 160 115 110 80 110 80 110 80 110 80 0 0 31 31 0 0 160 115 110 80 110 80 0 0 160 115 155 110 160 115 120 80 0 0 42 42 0 0 160 115 110 80 110 80 0 0 160 115 155 110 160 115 120 80 0 0 31 31 0 0 160 115 0 0 160 115 155 110 160 115 120 80 IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
No 1 2 3 4 5 6 7 8 9
Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY)
Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay
TdDAVId(RDY) DAV Rise to RDY Rise Delay TdRDY0(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV) RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width
10 TwRDY
11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. The VCC voltage specification of 3.0V guarantees 3.3V 0.3V and the VCC voltage specification of 5.5V guarantees 5.0V 0.5V.
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Z86C83/C84 Z8(R) MCU Microcontrollers Table 5. D/A Converter Electrical Characteristics VCC = 3.3V 10% Parameter Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25C Full Scale error at 25C Supply Range Power dissipation, no load Ref Input resistance Output noise voltage VDHI range at 3 volts VDLO range at 3 volts VDHI-VDLO, at 3 volts Capacitive output load, CL Resistive output load, RL Output slew rate
Notes: Voltage: 3.0V to 3.6V Temp: 0-70C
Minimum
3.0 2K 1.5 0.2 1.3 50K 1.0
Typical 8 0.25 0.25 1.5 10 0.25 3.3 10 4K 50 1.8 0.5 1.6
Maximum 1 0.5 3.0 20 0.5 3.6 10K 2.1 0.8 1.9 20
3.0
Units Bits LSB LSB sec mV LSB Volts mW Ohms Vp-p Volts Volts Volts pF Ohms V/sec
Table 6. D/A Converter Electrical Characteristics VCC = 5.0V 10% Parameter Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25C Full Scale error at 25C Supply Range Power dissipation, no load Ref Input resistance Output noise voltage VDHI range at 5 volts VDLO range at 5V volts VDHI-VDLO, at 5V volts Capacitive output load, CL Resistive output load, RL Output slew rate Minimum Typical 8 0.25 0.25 1.5 10 1 5.0 50 4K 50 Maximum 1 0.5 3.0 20 2 5.5 85 10K 3.5 1.7 2.7 30 3.0 Units Bits LSB LSB sec mV % FSR Volts mW Ohms Vp-p Volts Volts Volts pF Ohms V/sec
4.5 2K 2.6 0.8 0.9 20K 1.0
Notes: Voltage: 4.5V - 5.5V Temp: 0-70C The C84 Emulator has maximum setting time of 20 sec. (10 sec. typical).
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AC ELECTRICAL CHARACTERISTICS (Continued)
Table 7. A/D Converter Electrical Characteristics VCC = 3.3V 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25C Supply Range Power dissipation, no load Clock frequency Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI --VALO
Notes: Voltage: 3.0V to 3.6V Temp: 0-70C SCLK = System Clock on Bus Speed.
Minimum
Typical 8 0.5 0.5 3.3 20
Maximum 1 1 5.0 3.6 40 24 VAHI 35 X SCLK 40 AVCC AVCC-2.5 AVCC
3.0
VALO 4.3 25 VALO +2.5 ANGND 2.5
Units Bits LSB LSB mV Volts mW MHz Volts sec pF Volts Volts Volts
Table 8. A/D Converter Electrical Characteristics VCC = 5.0V 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25C Supply Range Power dissipation, no load Clock frequency Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI --VALO Minimum Typical 8 0.5 0.5 5.0 50 Maximum 1 1 45 5.5 85 33 VAHI 35 X SCLK 40 AVCC AVCC-2.5 AVCC Units Bits LSB LSB mV Volts mW MHz Volts sec pF Volts Volts Volts
4.5
VALO 4.3 25 VALO +2.5 ANGND 2.5
Notes: Voltage: 4.5V -5.5V Temp: 0-70C Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register. SCLK = System Clock on Bus Speed.
15
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Z86C83/C84 Z8(R) MCU Microcontrollers
PIN FUNCTIONS Application Precaution
The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above Vcc occur on the /RESET pin. Recommendations for dampening voltage surges in both test and OTP mode include the following:
s s
Using a clamping diode to /RESET Adding a capacitor to the affected pin
Port 2 (P27-P20) Port 2 is an 8-bit, bi-directional, CMOScompatible I/O port and an 8-channel muxed input to the 8-bit ADC. When configured as a digital input, by programming the Port2 Mode register, the Port 2 register can be evaluated to read digital data applied to Port 2, or the ADC result register can be read to evaluate the analog signals applied to Port 2 after configuring the ADC Control Registers. The direction of each of the eight Port 2 I/O lines can be configured individually (Figure 11). In addition, all four versions of the device provide the capability of connecting 10K (20%) pull-up resistors to each of the Port 2 I/O lines individually. The pull-ups are connected when activated through software control of P2RES register (Figure 67) when the corresponding Port 2 pin is configured to be an input. The pull-up resistor of a Port 2 I/O line is automatically disabled when the corresponding I/O is an output, regardless of the state of the corresponding P2RES bit value. Note: The Z86C83/C84 Emulator does not emulate the P2RES Register. Selection of the pull-ups are done via jumper settings on the emulator.
XTAL1. Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC network or an external single-phase clock to the on-chip oscillator input. XTAL2. Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC network to the on-chip oscillator output. Port 0 P00-P06. (P03-P06 is not available on the Z86C84). Port 0 is a 7-bit, bidirectional, CMOS-compatible I/O port. These seven I/O lines can be nibble programmable as P00-P03 input/output and P04-P06 input/output, separately (Figure 10). All input buffers are Schmitt-triggered and output drivers are push-pull. There is a ROM mask option to enable 100K (40%) pull-up resistors to Port 0, P00 to P02. Port 0 Auto Latch. (Auto Latch Mask Option available only on P00-P02. P03-P06 has the Auto Latches permanently enabled.) The Auto Latch provides valid CMOS Levels when P00-P06 (P00-P02 on C84) are selected as inputs and not externally driven. It is impossible to determine if a non-driven input is 1 or 0, however; the Auto Latch will sense the input condition and drive a valid CMOS level, thereby eliminating a floating mode that could cause excessive current. (Auto Latch is a ROM mask option for the Z86C83, Z86C84).
16
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Z86C83/C84 Z8(R) MCU Microcontrollers
PIN FUNCTIONS (Continued)
Port 0 (I/O)
/OEN
100K
ROM Mask Pull-Up Option (P00-P02 only)
Pad Out 1.5 In 2.3 Hysteresis
R
500 k
Notes: Auto Latch C83/E83: P00-P02 Mask Option P03-P06 Permanent C84/E84: P00 - P02 Mask Option
Figure 10. Port 0 Configuration
17
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Z86C83/C84 Z8(R) MCU Microcontrollers
P27 P26 P25 /C83 /C84 /E84 P24 P23 P22 P21 P20 Port 2 (I/O)
/OEN Data Input_en Select from P2RES
10K
Pad
P2
Analog Mux ADC
ADC0 (Bits 7, 6, 5)
Figure 11. Port 2 Configuration
18
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Z86C83/C84 Z8(R) MCU Microcontrollers
PIN FUNCTIONS (Continued)
Port 3 (P37-P30). Port 3 is a 6-bit, CMOS-compatible port, with three fixed inputs (P33-P31) and three fixed outputs (P34-P36), configured under software control for Input/Output, Counter/Timers, interrupt, and port handshake. P31, P32, and P33 are standard CMOS inputs (no Auto Latches). Pins P34, P35, and P36 are push-pull output lines (Figure 11). Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming Port 3 Mode Register (P3M bit 1). For Interrupt functions, Port 3, pin 3 is falling-edge interrupt input. P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and bit 7). P33 is the comparator reference voltage input when in Analog Mode. Access to Counter/Timers 1 is made through P31 (TIN) and P36 (TOUT). Handshake lines for Ports 0 and 2 are available on P31/P36 and P32/P35 (Table 9). Port 3 also provides the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); three external interrupt request signals (IRQ2-IRQ0); timer input and output signals (TIN and TOUT). Table 9. Port 3 Pin Assignments Pin P31 P32 P33 P34 P35 P36 I/O CTC1 Analog IN TIN AN1 IN AN2 IN REF OUT AN1-OUT OUT OUT TOUT Int. P0 HS P2 HS D/R Auto Latch. The Auto-Latch instruction puts valid CMOS levels on all CMOS inputs (except P33-P31) that are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Notes: 1. Deletion of Port Auto Latches is available as a ROM mask option. The Auto Latch Delete option is selected by the customer when the ROM code is submitted. 2. Ports 03, 04, 05, 07 have permanently enabled Auto Latches. Comparator Inputs. Port 3, P31 and P32, each have a comparator front end. The comparator reference voltage, P33, is common to both comparators. In analog mode, the P33 input functions as a reference voltage to the comparators. In Analog Mode, the internal P33 register and its corresponding IRQ1 is connected to the Stop-Mode Recovery source selected by the SMR register. In this mode, any of the Stop-Mode Recovery sources are used to toggle the P33 bit or generate IRQ1. In Digital Mode, P33 can be used as a Port 3 register input or IRQ1 source. P34 outputs the comparator outputs by software programming the PCON Register bit D0 to 1.
IRQ2 IRQ0 D/R IRQ1 R/D
R/D
Notes: HS = Handshake Signals D = /DAV R = RDY
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Z86C83/C84 Z8(R) MCU Microcontrollers
P36 P35 P34 Z86C83/C84 P33 P32 P31 Port 3 Port 3 (I/O)
R247 = P3M
D1
1 = Analog 0 = Digital
DIG. P31 (AN1) + AN IRQ2, TIN, P31 Data Latch
P32 (AN2) + P33 (REF) -
IRQ0, P32 Data Latch
From Stop-Mode Recovery Source
IRQ1, P33 Data Latch
Figure 12. Port 3 Input Configuration
20
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Z86C83/C84 Z8(R) MCU Microcontrollers
PIN FUNCTIONS (Continued)
Port Configuration Register (PCON). The PCON configures the ports individually for comparator output on Port 3. The PCON Register is located in the Expanded Register File at Bank F, location 00 (Figure 13). Bit 0 multiplexes comparator AN1 Output at P34. A "1" in this location brings the comparator output to P34 (Figure 14), and a "0" puts P34 into its standard I/O configuration. Note: Only comparator output AN1 is multiplexed to a Port 3 output. Comparator AN2 output is not connected to any pins. Note that the PCON Register is reset upon the occurrence of a WDT RESET (not in Stop Mode), and Power-On Reset (POR).
PCON (F) 00 D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3 0 P34 Standard Output* 1 P34 Comparator Output Reserved (Must be 1.) 0 Port 0 Open-Drain 1 Port 0 Push-Pull* Reserved (Must be 1.) * Default setting from Stop-Mode Recovery, Power-On Reset, and any WDT Reset.
Figure 13. Port Configuration Register (PCON) (Write-Only)
P34 OUT P31 AN1 + REF (P33)
P34 Normal PAD
PCON D0 0 P34 Standard Output 1 P34 Comparator Output * Reset Condition
*
Figure 14. Port 3 P34 Output Configuration
21
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Z86C83/C84 Z8(R) MCU Microcontrollers
FUNCTIONAL DESCRIPTION
RESET. (Input, Active Low). This pin initializes the MCU. Reset is accomplished either through Power-On Reset (POR), Watch-Dog Timer (WDT) Reset, or external reset. During POR, and WDT Reset, the internally generated reset is driving the reset pin Low for the POR time. Any devices driving the reset line must be open-drain to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. After the POR time, /RESET is a Schmitt-triggered input. After the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. Program execution begins at location 000C (hex), 5-10 TpC cycles after the RST is released. For POR, the reset output time is TPOR. Program Memory. C83/C84 can address up to 4 KB of internal Program Memory (Figure 15). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 13 to 4095 consist of on-chip, mask-programmed ROM. ROM Protect. The 4 KB of Program Memory is mask programmable. A ROM protect feature will prevent dumping of the ROM contents from an external program outside the ROM. Expanded Register File. The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space R0 through R15 is implemented as 16 groups of 16 registers per group (Figure 16). These register banks are known as the Expanded Register File (ERF). Bits 3-0 of the Register Pointer (RP) select the active ERF bank. Bits 7-4 of register RP select the working register group (Figure 17). Four system configuration registers reside in the ERF address space in Bank F and eight registers reside in Bank C. The rest of the ERF addressing space is not physically implemented, and is open for future expansion.
Interrupt Vector (Lower Byte)
Note: When using Zilog's Cross Assembler version 2.1 or earlier, use the LD RP, #0X instruction rather than the SRP #0X instruction to access the ERF.
2048/4096 Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 On-Chip ROM
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Figure 15. Program Memory Map
22
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\
23
Z8(R) ST ANDARD CONTROL REGISTERS
EXP ANDED REG. GROUP (F) REGISTER** RESET CONDITION
U U U 0 1 1 0 1
*
(F) 0F (F) 0E (F) 0D U U SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (F) 01 Reserved (F) 00 PCON 1 1 1 1 1 0 0 1 0 0 U U Reserved U WDTMR
U
0
0
REGISTER POINTER
7 6 (F) 0A (F) 09 (F) 08 (F) 07 5 4 3 2 1 0
(F) 0C
Z86C83/C84 Z8(R) MCU Microcontrollers
(F) 0B
0
0
0
Working Register Group Pointer
Expanded Register Group Pointer
RESET CONDITION REGISTER**
(F) 06 (F) 05 (F) 04 (F) 03 (F) 02 FF FE FD FC FB FA F9 F8 F7 F6 F5 P0 T0 P1 T1 TMR Reserved F4 F3 F2 F1 F0 P2M 7F Reserved P3M P01M IPR IRQ IMR FLAGS RP GPR SPL FF FO
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Register File**
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U U 0 U 1
U
U
U
U
U
U
U
FUNCTIONAL DESCRIPTION (Continued)
0
U
U
U
U
U
U
0
0
0
0
0
0
0
*
1
1
1
U
U
U
U
U
U
U
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
* *
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0 0
0
0
0
0
0
0
0
0
U
U
0
0
0
0
EXPANDED REG. GROUP (C) REGISTER
RESET CONDITION
Reserved
0F 00
(C) 0F (C) 0E (C) 0D
Reserved Reserved Reserved (C) 0C (C) 0B Reserved Reserved
U U U U U
U U U U U
U U U U U
U U U U U
U U U U U
U U U U U
U U U U U
0 U U U U
Figure 16. Expanded Register File Architecture
EXP ANDED REG. GROUP (0) REGISTER** RESET CONDITION
(0) 03 P3 P2 P1 P0 (0) 02 (0) 01 (0) 00 U U U U 1 U U U 1 U U U 1 U U U U U U U U U U U U U U U U U U U
Notes: U = Unknown
* Will not be reset with a Stop--Mode Recovery
** All addresses are in Hexadecimal
Will not be reset with a Stop-Mode Recovery, except Bit 0.
* *
(C) 0A (C) 09 (C) 08 (C) 07 (C) 06 (C) 05 (C) 04 (C) 03 (C) 02 (C) 01 (C) 00
ADR1 ADC1 ADC0 DAC2 DAC1 DACR2 DACR1 P2RES Reserved Reserved Reserved
U 0 1 U U 0 0 0 U U U
U U 1 U U 0 0 0 U U U
U U 1 U U 0 0 0 U U U
U U 0 U U 0 0 0 U U U
U U 0 U U 0 0 0 U U U
U U 0 U U U U 0 U U U
U U 0 U U U U 0 U U U
U U 0 U U U U 0 U U U
* * * * * * * *
DS96DZ80203
Z86C83/C84 Z8(R) MCU Microcontrollers
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer)
Expanded Register Group Working Register Group Note: Default Setting After Reset = 00000000
FF
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
R15 to R0
F0
Figure 17. Register Pointer Register
7F 70 6F 60 5F 50 4F
Register File. The Register File consists of three I/O port registers, 237 general-purpose registers, 15 control and status registers, and four system configuration registers in the Expanded Register Group (Figure 16). The instructions can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 18). In the 4-bit mode, the Register File is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Bank E0-EF is only accessed through working registers and indirect addressing modes. CAUTION: D4 of Control Register P01M (R251) must be 0. R254. The C83/C84 has one extra general-purpose register located at FEH (R254). It is set to 00H after any reset. Stack. The C83/C84 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 236 general-purpose registers. Register R254 cannot be used for stack. General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. It will not keep its last state from a VLV reset if the VCC drops below 1.8V. This includes Register R254. Note: Register Bank E0-EF is only accessed through working register and indirect addressing modes.
40 3F 30 2F 20 1F
Specified Working Register Group
The lower nibble of the register file address provided by the instruction points to the specified register.
Register Group 1
10 0F
R15 to R0 R15 to R4* R3 to R0*
Register Group 0* I/O Ports*
00
* Expanded Register File Bank (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP).
Figure 18. Register Pointer
RAM Protect. The upper portion of the RAM's address spaces %80F to %EF (excluding the control registers) are protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or 1 into the Interrupt Mask (IMR) register, bit D6. A 1 in D6 enables RAM Protect.
24
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Z86C83/C84 Z8(R) MCU Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 19). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divide-by-four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers can be cascaded by connecting the T0 output to the input of T1. TIN Mode is enabled by setting R243 PRE1 Bit D1 to 0.
OSC Internal Data Bus Write /2 PRE0 Initial Value Register D0 (SMR) 6-Bit Down Counter 8-bit Down Counter T0 Initial Value Register T0 Current Value Register Write Read
D1 (SMR)
/16
/4
IRQ4
Internal Clock External Clock Clock Logic /4
/2
TOUT P36
6-Bit Down Counter
8-Bit Down Counter
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
T1 Initial Value Register Read
T1 Current Value Register
TIN P31
Internal Data Bus
Figure 19. Counter/Timer Block Diagram
25
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Z86C83/C84 Z8(R) MCU Microcontrollers Interrupts. The Z8 has six different interrupts from six different sources. These interrupts are maskable, prioritized (Figure 20) and the six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, and two in counter/timers (Table 10). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. This action disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt.
IRQ0 IRQ2 IRQ1, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7)
IRQ
IMR 6 IPR
Global Interrupt Enable Interrupt Request
PRIORITY LOGIC
Vector Select
Figure 20. Interrupt Block Diagram
Table 10. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1, IRQ2 IRQ3 IRQ4 IRQ5 Source /DAV0, IRQ0 IRQ1 /DAV2, IRQ2, TIN IRQ3 T0 T1 Vector Location 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 Comments External (P32), Rise/ Fall Edge Triggered External (P33), Fall Edge Triggered External (P31), Rise /Fall Edge Triggered By User Software Internal Internal
26
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Z86C83/C84 Z8(R) MCU Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Programming bits for the Interrupt Edge Select is located in the IRQ Register (R250), bits D7 and D6. The configuration is shown in Table 11. Table 11. IRQ Register IRQ D7 0 0 1 1 D6 0 1 0 1 Interrupt Edge P31 P32 F F F R R F R/F R/F Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 16 MHz max., with a series resistance (RS) of less than or equal to 100 Ohms when clocking from 1 MHz to 16 MHz. The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to the device Ground pin to reduce Ground noise injection into the oscillator. Note: For better noise immunity, the capacitors should be tied directly to the device Ground pin (VSS).
Notes: F = Falling Edge R = Rising Edge
XTAL1 C1 VSS* * XTAL2 C2 VSS* * Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * f = 8 MHz C2 VSS* * LC C1, C2 = 22 pF L = 130 uH * f = 3 MHz * C1 VSS* * L
XTAL1
XTAL1
XTAL2
XTAL2
External Clock
* Preliminary value including pin parasitics * * Device ground pin
Figure 21. Oscillator Configuration
27
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Z86C83/C84 Z8(R) MCU Microcontrollers
Analog-to-Digital Converter
The Analog-to-Digital (ADC) is an 8-bit half flash converter that uses two reference resistor ladders for its upper 4 bits (MSBs) and lower 4 bits (LSBs) conversion. Two reference voltage pins, AVCC and AGND, are provided for external reference voltage supplies. During the sampling period from one of the eight channel inputs, the converter is also being auto-zeroed before starting the conversion. The conversion time is dependent on the internal clock frequency. The minimum conversion time is 35 X SCLK(see Figure 22). The ADC is controlled by the Z8(R) and its three registers (two Control and one Result) are mapped into the Extended Register File. A conversion can be initiated by writing to the ADC Control Register 0 after the ADC Control Register 1 is configured. The start command is implemented in such a way as to begin a conversion at any time, if a conversion is in progress and a new start command is received, then the conversion in progress will be aborted and a new conversion will be initiated. This allows the programmed values to be changed without affecting a conversion-inprogress. The new values will take effect only after a new start command is received. The ADC can be disabled (for low power) or enabled by a Control Register bit. Though the ADC will function for a smaller input voltage and voltage reference, the noise and offsets remain constant over the specified electrical range. The errors of the converter will increase and the conversion time may also take slightly longer due to smaller input signals.
ADC Calibration Offset
Specially matched resistors are program-enabled to allow 35.0 percent or 50 percent offset from AGND. They may selectively enable these resistors to offset the AGND by 35.0 percent (2.5V to 5V) or 50 percent (1.75V to 5V) thereby allowing the 8-bit ADC across a narrower voltage range. This will allow significant resolution improvement within the reduced voltage range. Note: The AVCC must be the same value as VCC and AGND must be the same value as GND.
EXT
Start Converter 8 A/D Control Reg. ADC0 Vref + Vcc A/D Result Reg. ADR1 Vref GND AGND A/D Converter Sample and Hold AVCC
8
8
A/D Control Reg. ADC1
4 Selected Channel
ADC Register 9 D4, D5
Calibration Offset
Figure 22. ADC Architecture
28
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Z86C83/C84 Z8(R) MCU Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
ADC0 (A) Bank C, Register 8 D7 D6 D5 D4 D3 D2 D1 D0 CSEL0 CSEL1 CSEL2 SCAN 0 = No action. * 1 = Convert, then stop. AIN/Input/Output Control 0 = No action * 1 = Enable selected channel (D2,D1,D0) as analog input on associated Port 20-27 Must be D7 = 0 D6 = 0 D5 = 1
ADE (bit 7). A zero disables any A/D conversions or accessing any ADC registers except writing to ADE bit. A one Enables all ADC accesses. ADC result register is shown in Figure 25.
ADR Bank C, Register A D7 D6 D5 D4 D3 D2 D1 D0
Data
* Default After Reset
Figure 25. Result Register (Read-Only) Figure 23. ADC Control Register 0 (Read/Write)
SCAN 0 1 No action* Convert channel then stop
Reg F Reg E Reg D Reg C Reg B Channel 0 (P20)* 1 (P21) 2 (P22) 3 (P23) 4 (P24) 5 (P25) 6 (P26) 7 (P27) Reg A Reg 9 Reg 8 Reg 7 Reg 6 Reg 5 Reg 4 Reg 3 Reg 2 Reg 1 Reg 0 AD Result 1 AD Control 1 AD Control 0
Channel Select (bits 2, 1, 0). CSEL2 0 0 0 0 1 1 1 1 CSEL1 0 0 1 1 0 0 1 1 CSEL0 0 1 0 1 0 1 0 1
These registers can be accessed.
Note: *The desired P2 bit must be set equal 1 to allow Port bit ias ADC input.
ADC1 Bank C, Register 9 D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. Bank C
Must be 0. D5 0 1 0 1 D4 0 0 1 1 50 % AGND Offset 35% AGND Offset Reserved No Offset
Reserved (Must be 1.) ADE 0 Disable* 1 Enable
Figure 24. ADC Control Register 1 (Read/Write)
29
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Z86C83/C84 Z8(R) MCU Microcontrollers Figure 27 shows the input circuit of the ADC. When conversion starts the analog input voltage is connected to the MSB and LSB flash converter inputs as shown in the Input Impedance CKT diagram. Effectively, shunting 31 parallel internal resistance of the analog switches and simultaneously charging 31 parallel 0.5 pF capacitors, which is equivalent to seeing a 400 Ohms input impedance in parallel with a 16 pF capacitor. Other input stray capacitance adds about 10 pF to the input load. For input source resistances up to 2 kOhms can be used under normal operating condition without any degradation of the input settling time. For larger input source resistance, longer conversion cycle time may be required to compensate the input settling time problem.
CMOS Switch on Resistance 2-5k
V Ref R Source V Ref C Parasitic V Ref
C .5 pF 31 CMOS Digital Comparators
C .5 pF
C .5 pF
Figure 27. Input Impedance of ADC
Typical Z8 A/D Conversion Sequence
1. Set the register pointer to Extended Bank (C),that is, SRP #%0C instruction. 2. Next, set ADE flag by loading ADC1 Control Register Bank (C) Register 9, bit 7. Also, load bits 0-4 of this same register to select a AVCC or AGND offset value. A precision voltage divider connected to the A/D resistive ladder can offset conversion dynamic range to specified limits within the AVCC and AGND limits. By loading Bank (C) Register 9, bits 0-4, with the appropriate value it is possible to select from these groups: a. No Offset. The Converter Dynamic range is from 0V to 5.0V for AVCC = 5.0V. b. 35 Percent AGND Offset. The Converter Dynamic range is 1.75V - 5.0V for AVCC = 5.0V. c. 50 Percent AGND Offset. The Converter Dynamic range is 2.5V - 5.0V for AVCC = 5.0V. 3. Select one of the eight A/D inputs for conversion by loading Bank (C) Register 8 with the desired attributes: Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D conversion (or digital port I/O). 4. Set Bank (C) Register 8, bit 3 to enable A/D conversion. (This flag can be set concurrently with step 3.) This flag is automatically reset when the A/D conversion is completed, so a bit test can be performed to determine A/D readiness if necessary. 5. Read the A/D result in Bank (C) Register A. Please note that the A/D result is not valid (indeterminate) unless ADE flag (Register 9, bit 7) was previously set, otherwise A/D converter output is tri-stated.
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FUNCTIONAL DESCRIPTION (Continued) Digital-to-Analog Converters
The Z86C84 has two Digital-to-Analog Converters (DACs). Each DAC is an 8-bit resistor string, with a programmable 0.25X, 0.5X, or 1X gain output buffer. The DAC output voltage settles after the internal data is latched into the DAC Data register. The top and bottom ends of the resistor ladder are register-selected to be connected to either the analog supply rails, AVCC and AGND, or two externally-provided reference voltages, VDHI and VDLO. External references are recommended to explicitly set the DAC output limits. Since the gain stage cannot drive to the supply rails, VDHI and VDLO must be within ranges shown in the specifications. If either reference approaches the analog supply rails, the output will be unable to span the reference voltage range. The externally provided reference voltages should not exceed the supply voltages. The DAC outputs are latch-up protected and can drive output loads (Figure 28). Note: The AVCC must be the same value as VCC and AGND must be the same value as GND
PAD VDHI
AVCC 8 Data Bus 8 DACRn Control Register (n = 1 or 2) DACn Data Register 8 High Analog
DAC1 or DAC2 PAD
8-Bit Resistor Ladder Low
+ AGND Programmable Gain
* Bits 0, 1
Note: * DACRn Control Register Bits
PAD VDLO
Figure 28. DAC Block Diagram
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Z86C83/C84 Z8(R) MCU Microcontrollers The D/A conversion for DAC1 is driven by writing 8-bit data to the DAC1 data register (Bank C, Register 06H). The D/A conversion for DAC 2 is controlled by the DAC2 data register (Bank C, Register 07H). Each DAC data register is initialized to midrange 80H on power-up. There are two DAC control registers: DACR1 (Bank C, Register 04H) for DAC1, and DACR2 (Bank C, Register 05H) for DAC2. Control register bits 0 and 1 set the DAC gain. When DAC data is 80H, the DAC output is constant for any gain setting (Figure 29 and Figure 31).
DACR2 Bank C, Register 5 D7 D6 D5 D4 D3 D2 D1 D0 DAC2 Gain 0 0 1X 0 1 1/2 X 1 0 1 Not Used 1 1 1/4 X DAC2 Enable 0 Disable 1 Enable Reserved (Must be 0)
Figure 31. D/A 2 Control Register
DACR1 Bank C, Register 4 D7 D6 D5 D4 D3 D2 D1 D0 DAC1 Gain 0 0 1X 0 1 1/2 X 1 0 1 Not Used 1 1 1/4 X DAC1 Enable 0 Disable 1 Enable Reserved (Must be 0)
DAC2 Bank C, Register 7 D7 D6 D5 D4 D3 D2 D1 D0 = Low Level = High Level
Figure 32. D/A 2 Data Register
Figure 29. D/A 1 Control Register
DAC1 Bank C, Register 6 D7 D6 D5 D4 D3 D2 D1 D0 0 = Low Level 1 = High Level
Figure 30. D/A 1 Data Register
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FUNCTIONAL DESCRIPTION (Continued)
DAC Output in Volts 3.5V VDHI 3.5
3.05 2% accuracy 2.6
2.15
2.15
1.7
1/4X 1/2X 1X
1.26
VDLO .8
0
Notes: Vcc = 5.0V 10% VDHI = 3.5V VDLO = 0.8V
80H DAC Data Register Value
FFH
Figure 33. Gain Control on DAC
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator or by the XTAL oscillator is used for the POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions:
s s s
Power Fail to Power OK Status Stop-Mode Recovery (If D5 of SMR Register = 1) WDT Time-Out (Including from Stop Mode)
HALT. Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated (a POR or a WDT time-out). An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. In case of a POR or a WDT time-out, program execution will restart at address 000CH. STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A (typical) or less. The STOP mode is terminated by a reset of either WDT time-out, POR, or Stop-Mode Recovery. This causes the processor to restart the application program at address 000CH.
The POR time is TPOR minimum. Bit 5 of the STOP Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, and RC/LC oscillators with fast start up time).
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Z86C83/C84 Z8(R) MCU Microcontrollers In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode = FFH) immediately before the appropriate sleep instruction, that is, FF 6F FF 7F NOP STOP NOP HALT ; clear the pipeline ; enter STOP mode or ; clear the pipeline ; enter HALT mode
SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Stop-Mode Recovery Source 2 00 POR only* 01 AND P20,P21,P22,P23 10 AND P20,P21,P22,P23, P24,P25,P26,P27 Reserved (Must be 0) Note: Not used in conjunction with SMR Source
Figure 35. Stop-Mode Recovery Register 2 ([0F] DH: Write-Only)
STOP-Mode Recovery (SMR) Register. This register selects the clock divide value and determines the mode of STOP-Mode Recovery (Figure 34 and Figure 35). All bits are Write-Only, except bit 7, which is Read-Only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, or the SMR Register, specify the source of the STOP-Mode Recovery signal. Bits 0 and 1 determine the timeout period of the WDT. The SMR Register is located in Bank F of the Expanded Register Group at address 0BH. When the Stop-Mode Recovery sources are selected in this register, then SMR2 Register bits D0,D1 must be set to 0.
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The control selectively reduces device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). This bit is reset to D0 = 0 after a Stop-Mode Recovery, WDT Timeout, and POR. External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. Maximum external clock frequency is 4 MHz when SMR Bit D1 = 1 where SCLK/TCLK = XTAL.
SMR (FH) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF* * 1 ON External Clock Divide-by-2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL Stop-Mode Recovery Source 000 POR Only and/or External Reset* 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level 0 Low * 1 High Stop Flag (Read-Only) 0 POR * 1 Stop Recovery
OSC SMR, D1
/2
Note: Not used in conjunction with SMR2 Source * Default Setting After RESET ** Default setting after RESET and Stop-Mode Recovery
/ 16
SCLK SMR, D0 TCLK
Figure 34. STOP-Mode Recovery Register (WriteOnly Except Bit D7, Which Is Read-Only)
Figure 36. SCLK Circuit
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FUNCTIONAL DESCRIPTION (Continued)
STOP-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake-up source of the STOP recovery (Figure 37 and Table 12). When the STOP-Mode Recovery Sources are selected in this register then SMR2 register bits D0,D1 must be set to zero. P33-P31 cannot wake up from Stop Mode if the input lines are configured as analog inputs to the Analog comparator or Analog-to-Digital Converter since the Analog Comparator's are powered down in Stop Mode. Note: If the Port 2 pin is configured as an output, this output level will be read by the SMR circuitry. Table 12. STOP-Mode Recovery Source SMR:432 D4 D3 D2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition (not in Analog Mode) P32 transition (not in Analog Mode) P33 transition (not in Analog Mode) P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 STOP-Mode Recovery Edge Select (D6). A "1" in this bit position indicates that a high level on the output to the exclusive Or-Gate input from the selected recovery source wakes the Z86C83/C84 from STOP mode. A "0" indicates low-level recovery. The default is 0 on POR. This bit is used for either SMR or SMR2. Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A 0 in this bit (cold) indicates that the device resets by POR/WDT reset. A "1" in this bit (warm) indicates that the device awakens by a Stop-Mode Recovery source. Note: A WDT reset out of Stop Mode will also set this bit to a "1." STOP-Mode Recovery Register 2 (SMR2). This register contains additional Stop-Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR Register Bits D2, D3, and D4 must be 0. Table 13. Stop-Mode Recovery Source SMR:10 D1 D0 0 0 0 1 1 0 Operation Description of Action SMR2 disables source Logical AND of P20 through P23 Logical AND of P20 through P27
STOP-Mode Recovery Delay Select (D5). This bit, if High, enables the TPOR /RESET delay after Stop-Mode Recovery. The default configuration of this bit is "1". A POR or WDT reset will override the selection and cause the reset delay to occur.
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SMR2 D1 D0 11 P20 P20
SMR2 D1 D0 11
P23
P27
SMR D4 D3 D2 000 VDD SMR D4 0 0 0 P31 P32 D3 0 1 1 D2 SMR D4 D3 D2 1 100 0 1 P27 P23 P27 SMR D4 D3 D2 101 P20 SMR D4 D3 D2 110 P20 SMR D4 D3 D2 111
P33
T POR o RESET Stop-Mode Recovery Edge Select (SMR) T P33 Data o Latch and IRQ1 P33 From Pads
MUX
Digital/Analog Mode Select (P3M)
Figure 37. STOP-Mode Recovery Source
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FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The POR clock source is selected with bit 4 of the WDT register (Figure 38). WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The WDTMR must be written to within 64 internal system clocks. After that, the WDTMR is write protected. Note: WDT time-out while in Stop-Mode will not reset SMR, PCON, WDTMR, P2M, P3M, Ports 2 and 3 Data Registers, but will cause the reset delay to occur. The Power-On Reset (POR) clock source is selected with bit 4 of the WDTMR. Bits 0 and 1 control a tap circuit that determines the time-out period. Bit 2 determines whether the WDT is active during HALT and bit 3 determines WDT activity during STOP. If bits 3 and 4 of this register are both set to "1," the WDT is only driven by the external clock during STOP mode. This feature makes it possible to wake up from STOP mode from an internal source. Bits 5 through 7 of the WDTMR are reserved (Figure 39). This register is accessible only during the first 64 processor cycles (64 SCLKs) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset or a Stop-Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register group at address location 0FH.
/RESET Clear CLK 18 Clock RESET Generator RESET
Internal RESET
WDT Select (WDTMR) CK Source Select (WDTMR) XTAL RC OSC. M U X 128 SCLK POR CK CLR
WDT TAP SELECT
128 256 512 2048 SCLK SCLK SCLK SCLK WDT/POR Counter Chain
VCC 3.0V REF . WDT
+ -
3.0V Operating Voltage Det.
From Stop Mode Recovery Source
12 ns Glitch Filter
Stop Delay Select (SMR D5)
Figure 38. Resets and WDT
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WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0
1. If WDT is permanently selected (always ON mode), the WDT will continue to run even if set not to run in STOP or HALT Mode.
WDT TAP 00 256 01 512 10 1024 11 4096 SCLK SCLK * SCLK SCLK
2. WDT instructions affect the Z (Zero), S (Sign), and V (Overflow) flags. On-Board, Power-On-Reset RC or External XTAL1 Oscillator Select (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a "1," the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator. If the XTAL1 pin is selected as the oscillator source for the WDT, during Stop Mode, the oscillator will be stopped and the WDT will not run. This is true even if the WDT is selected to run during Stop Mode. VCC Voltage Comparator. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. RESET is globally driven if VCC is below the specified voltage (typically 2.6V). ROM Protect. ROM Protect is mask-programmable. It is selected by the customer at the time the ROM code is submitted.
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0)
* Default setting after RESET
XTAL=SCLK/TCLK shown
Figure 39. Watch-Dog Timer Mode Register (Write Only)
WDT Time Select (D1, D0). Selects the WDT time-out period. It is configured as shown in Table 14. Table 14. WDT Time Select (Min. @ 5.0V) D1 0 0 1 1 D0 0 1 0 1 Time-Out of Internal RC OSC 6.25 ms min 12.5 ms min 25 ms min 100 ms min Time-Out of SCLK Clock 256 SCLK 512 SCLK* 1024 SCLK 4096 SCLK
ROM Mask Selectable Options
There are six ROM mask options that must be selected at the time the ROM mask is ordered (ROM code submitted). Table 15. ROM Mask Selectable Options Option Permanent WDT Port0 Pull-Ups Port0 Auto Latches ROM Protect RAM Protect Selection Yes/No Yes/No Yes/No Yes/No Yes/No
Notes: The default on a WDT initiated reset is 512 SCLK. The minimum time shown is for VCC @ 5.0V.
WDT During HALT (D2). This bit determines whether or not the WDT is active during HALT mode. A "1" indicates active during HALT. The default is "1." Note: If WDT is permanently selected (always ON mode), the WDT will continue to run even if set not to run in STOP or HALT Mode. WDT During STOP (D3). This bit determines whether or not the WDT is active during STOP mode. Since XTAL clock is stopped during STOP mode, unless as specified below, the on-board RC has to be selected as the clock source to the POR counter. A "1" indicates active during STOP. The default is "1". If bits D3 and D4 are both set to "1," the WDT only, is driven by the external clock during STOP mode.
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EXPANDED REGISTER FILE CONTROL REGISTERS (0C)
ADC0 (OC) 8H D7 D6 D5 D4 D3 D2 D1 D0 Channel Select (bits 2,1,0) CSEL2 CSEL1 CSEL0 Channel 0 0 0 0* 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Scan 0 = No action.* 1 = Convert channel then stop. AIN/Input/Output Control 0 = No Action (Digital Function)* 1 = Enable Selected Channel (M2, M1, M0) as analog input on associated Port P27-P20
Must be 0 0 1
DACR1 Bank C, Register 4 D7 D6 D5 D4 D3 D2 D1 D0 DAC1 Gain 0 0 1X 0 1 1/2 X 1 0 1 Not Used 1 1 1/4 X DAC1 Enable 0 Disable 1 Enable Reserved (Must be 0)
1
Figure 43. D/A 1 Control Register
* Default setting after reset.
DACR2 Bank C, Register 5
Figure 40. ADC Control Register 0 (Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DAC2 Gain 0 0 1X 0 1 1/2 X 1 0 1 Not Used 1 1 1/4 X
ADC1 Bank C, Register 9 D7 D6 D5 D4 D3 D2 D1 D0
DAC2 Enable 0 Disable 1 Enable Reserved (Must be 0)
Must be 0. D5 0 1 0 1 D4 0 0 1 1 50 % AGND Offset 35% AGND Offset Reserved No Offset
Figure 44. D/A 2 Control Register
Reserved (Must be 1.) ADE 0 Disable* 1 Enable
DAC1 Bank C, Register 6 D7 D6 D5 D4 D3 D2 D1 D0
Figure 41. ADC Control Register 1 (Read/Write)
0 = Low Level 1 = High Level
Figure 45. D/A 1 Data Register
ADR1 (OC) AH D7 D6 D5 D4 D3 D2 D1 D0
DAC2 Bank C, Register 7
Data
D7 D6 D5 D4 D3 D2 D1 D0 0 = Low Level 1 = High Level
Figure 42. AD Result Register (Read Only)
Figure 46. D/A 2 Data Register
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Z86C83/C84 Z8(R) MCU Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS
( ) D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF* * 1 ON External Clock Divide-by-2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL Stop-Mode Recovery Source 000 POR Only and/or External Reset* 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level 0 Low * 1 High Stop Flag (Read-Only) 0 POR * 1 Stop Recovery D7 D6 D5
WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 256 01 512 10 1024 11 4096
SCLK SCLK * SCLK SCLK
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0)
Note: Not used in conjunction with SMR2 Source * Default Setting After RESET ** Default setting after RESET and Stop-Mode Recovery
* Default setting after RESET
XTAL=SCLK/TCLK shown
Figure 47. Stop-Mode Recovery Register (Write-Only, except Bit 7 which is Read-Only)
Figure 49. Watch-Dog Timer Mode Register (Write-Only)
PCON (F) 00
SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Stop-Mode Recovery Source 2 00 POR only* 01 AND P20,P21,P22,P23 10 AND P20,P21,P22,P23, P24,P25,P26,P27 Reserved (Must be 0) Note: Not used in conjunction with SMR Source
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3 0 P34 Standard Output* 1 P34 Comparator Output Reserved (Must be 1.) 0 Port 0 Open-Drain 1 Port 0 Push-Pull* Reserved (Must be 1.) * Default setting from Stop-Mode Recovery, Power-On Reset, and any WDT Reset.
Figure 48. Watch-Dog Timer Mode Register 2
Figure 50. Port Configuration Register (PCON) (Write-Only)
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Z86C83/C84 Z8(R) MCU Microcontrollers
Z8 CONTROL REGISTERS
R240 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T1 Single Pass 1 T1 Modulo Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0
1
Reserved (Must be 0)
Figure 51. Reserved
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. Prescaler 1 Register (F3H: Write-Only)
0 No Function 1 Load T0 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T1 0 Disable T1 Count 1 Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Reserved (Must be 0)
R244 T0 D7 D6 D5 D4 D3 D2 D1 D0
T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When READ)
Figure 55. Counter/Timer 0 Register (F4H: Read/Write)
Figure 52. Timer Mode Register (F1H: Read/Write)
R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T0 Single Pass 1 T0 Modulo N Reserved (Must be 0.)
T1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T1 Current Value (When READ)
Prescaler Modulo (Range: 1-64 Decimal 01-00 Hex)
Figure 56. Prescaler 0 Register (F5H: Write-Only) Figure 53. Counter/Timer 1 Register (F2H: Read/Write)
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Z86C83/C84 Z8(R) MCU Microcontrollers
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain* 1 Port 2 Push-Pull Port 3 Inputs 0 Digital* 1 Analog Reserved (Must be 0) *Default Setting After Reset
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5
Figure 57. Port 3 Mode Register (F7H: Write-Only)
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
P27- P20 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT* *Default Setting After Reset
Figure 60. Interrupt Priority Register (F9H: Write-Only)
Figure 58. Port 2 Mode Register (F6H: Write-Only)
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
Default Setting After Reset = 00H
IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = Software Controlled IRQ4 = T0 IRQ5 = T1 Inter Edge 00 P31 01 P31 10 P31 11 P31 P32 P32 P32 P32
P00-P03 Mode 00 Output 01 Input * 1X A11-A8 Reserved (Must be 1) Reserved (Must be 0) P04-P06 Mode 00 Output 01 Input * 1X A15-A12
R251 IMR
Figure 61. Interrupt Request Register (FAH: Read/Write)
Not available for Z86C82, but must be set to 00.
Figure 59. Port 0 and 1 Mode Register (F8H: Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5-IRQ0 (D0 = IRQ0) 1 0 1 0 RAM Protect Enabled RAM Protect Disabled * Enables Interrupts Disable interrupts * * (Default setting after RESET.)
This option must be selected when ROM code is submitted for Rom Masking; otherwise, this control bit is disabled permanently.
Figure 62. Interrupt Mask Register (FBH: Read/Write)
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Z86C83/C84 Z8(R) MCU Microcontrollers
Z8 CONTROL REGISTERS (Continued)
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0
R254 GPR D7 D6 D5 D4 D3 D2 D1 D0 0 = Low Level 1 = High Level Default Setting After Reset = 00H
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 65. General-Purpose Register (FEH: Read/Write)
Figure 63. Flag Register (FCH: Read/Write)
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
R253
RP
Default Setting After Reset = 00H
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Lower Byte (SP7-SP0) 0 = Low Level 1 = High Level
Expanded Register Group Working Register Group Note: Default Setting After Reset = 00000000
Figure 66. Stack Pointer (FFH: Read/Write)
Figure 64. Register Pointer (FDH: Read/Write)
P2RES Bank C, Register 3 D7 D6 D5 D4 D3 D2 D1 D0
Port 2 (P27-P20) 10K Pull-up 0 = Disabled 1 = Enabled
Figure 67. Port 2 Pull-up Register
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Z86C83/C84 Z8(R) MCU Microcontrollers
PACKAGE INFORMATION
Figure 68. 28-Pin DIP Package Diagram
Figure 69. 28-Pin SOIC Package Diagram
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Z86C83/C84 Z8(R) MCU Microcontrollers
1
Figure 70. 28--Pin PLCC Package Diagram
DS96DZ80203
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Z86C83/C84 Z8(R) MCU Microcontrollers
ORDERING INFORMATION
Z86C83 16 MHz 28-Pin DIP Z86C8316PSC Z86C8316PEC Z86C84 16 MHz 28-Pin DIP Z86C8416PSC Z86C8416PEC
28-Pin SOIC Z86C8316SSC Z86C8316SEC
28-Pin PLCC Z86C8316VSC Z86C8316VEC
28-Pin SOIC Z86C8416SSC Z86C8416SEC
28-Pin PLCC Z86C8416VSC Z86C8416VEC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
CODES Package
P = Plastic DIP S = Plastic SOIC
Temperature
S = 0 C to + 70 C E = -40C to +105C
Speed
16 = 16 MHz
Environmental
C = Plastic Standard Example: Z 86C83 16 P S C
is a Z86C83, 16 MHz, DIP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
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DS96DZ80203

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